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Preliminary Information
VCSO FEC PLL FOR SONET/OTN
PIN ASSIGNMENT (9 x 9 mm SMT)
FIN_SEL1 GND P_SEL2 DIF_REF0 nDIF_REF0 REF_SEL DIF_REF1 nDIF_REF1 VCC FIN_SEL0 FEC_SEL0 FEC_SEL1 LOL NBW VCC DNC DNC DNC 27 26 25 24 23 22 21 20 19
M2060/61/62 M2065/66/67
GENERAL DESCRIPTION
The M2060/61/62 and M2065/66/67 are VCSO (Voltage Controlled SAW Oscillator) based clock PLLs designed for FEC clock ratio translation in 10Gb optical systems such as OC-192 or 10GbE. They support FEC (Forward Error Correction) clock multiplication ratios, both forward (mapping) and inverse (de-mapping). Multiplication ratios are pin-selected from pre-programming look-up tables.
FEATURES
Integrated SAW delay line; Output of 15 to 700 MHz * Low phase jitter < 0.5 ps rms typical (12kHz to 20MHz or 50kHz to 80MHz) Pin-selectable PLL divider ratios support FEC ratios
* M2060/65: OTU1 (255/238) and OTU2 (255/237) Mapping * M2061/66: OTU1 (238/255) or OTU2 (237/255) De-mapping * M2062/67: OTU1 (238/255) and OTU2 (237/255) De-mapping
28 29 30 31 32 33 34 35 36
M2060 Series
(Top View)
18 17 16 15 14 13 12 11 10
P_SEL0 P_SEL1 nFOUT0 FOUT0 GND nFOUT1 FOUT1 VCC GND
Figure 1: Pin Assignment
LVPECL clock output (CML and LVDS options available) Reference clock inputs support differential LVDS, LVPECL, as well as single-ended LVCMOS, LVTTL Loss of Lock (LOL) output pin Narrow Bandwidth control input (NBW pin) to adjust loop bandwidth Hitless Switching (HS) options with or without Phase Build-out (PBO) available to enable SONET (GR-253) /SDH (G.813) MTIE and TDEV compliance during reference clock reselection Single 3.3V power supply Small 9 x 9 mm SMT (surface mount) package
Example I/O Clock Frequency Combinations
Using M2061-11-622.0800 FEC De-Map Ratios FEC De-Map PLL Ratio Mfec / Rfec 1/1 237/255 238/255 Base Input Rate 1 (MHz) 622.0800 666.5143 669.3266 Output Clock (either output) MHz 622.08 or 155.52
Table 1: Example I/O Clock Frequency Combinations
Note 1: Input reference clock can be the base frequency shown divided by "Mfin" (as shown in Tables 3 and 4 on pg. 3). * Specify VCSO center frequency at time of order.
SIMPLIFIED BLOCK DIAGRAM
Loop Filter
M2060 Series
NBW LOL
MUX
DIF_REF0 nDIF_REF0 DIF_REF1 nDIF_REF1 REF_SEL FEC_SEL1:0 FIN_SEL1:0 P_SEL2:0
2
0 1
Rfec Div
Phase Detector
VCSO
Mfec Div
Mfec and Rfec Divider LUT Mfin Divider LUT
(1, 4, 8, 32) or ( 1, 4, 8, 16)
Mfin Div
GND GND GND OP_IN nOP_OUT nVC VC OP_OUT nOP_IN
1 2 3 4 5 6 7 8 9
P Divider
FOUT0: 1, 4, 8, 32 or TriState FOUT1: 1, 4, 8 or TriState
TriState
FOUT0 nFOUT0 FOUT1 nFOUT1
2
3
P Divider LUT
Figure 2: Simplified Block Diagram
M2060/61/62 M2065/66/67 Datasheet Rev 0.4
M2060/61/62 VCSO FEC PLL for SONET/OTN
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M2060/61/62, M2065/66/67
VCSO FEC PLL FOR SONET/OTN
Preliminary Information
PIN DESCRIPTIONS
Number 1, 2, 3, 10, 14, 26 4 9 5 8 6 7 11, 19, 33 12 13 15 16 17 18 25 20 21 22 23 24 27 28 29 30 31 Name GND OP_IN nOP_IN nOP_OUT OP_OUT nVC VC VCC FOUT1 nFOUT1 FOUT0 nFOUT0 P_SEL1 P_SEL0 P_SEL2 nDIF_REF1 DIF_REF1 REF_SEL nDIF_REF0 DIF_REF0 FIN_SEL1 FIN_SEL0 FEC_SEL0 FEC_SEL1 LOL I/O Configuration Description
Ground Input Output Input Power Output Output Input Input Input Input Input Input No internal terminator No internal terminator
Power supply ground connections. External loop filter connections. See Figure 5, External Loop Filter, on pg. 8. Power supply connection, connect to +3.3V. Clock output pair 1. Differential LVPECL. Clock output pair 0. Differential LVPECL.
, P divider selection. LVCMOS/LVTTL. See Table 8, Internal pull-down resistor1 Post-PLL Look-Up Table (LUT), on pg. 4. P Divider Reference clock input pair 1. Differential LVPECL or LVDS. Internal pull-down resistor1 Resistor bias on inverting terminal supports TTL or LVCMOS. Internal pull-down resistor1 Biased to Vcc/2 2 Internal pull-down resistor 1 Reference clock input selection. LVCMOS/LVTTL: Logic 1 selects DIF_REF1, nDIF_REF1. Logic 0 selects DIF_REF0, nDIF_REF0. Reference clock input pair 0. Differential LVPECL or LVDS. Resistor bias on inverting terminal supports TTL or LVCMOS. Biased to Vcc/2 2
Internal pull-down resistor1 Input clock frequency selection. LVCMOS/LVTTL. Seepg. 3. Tables 3 and 4 Mfin Divider Look-Up Tables (LUT) on Mfec and Rfec divider value selection. LVCMOS/ LVTTL. Internal pull-down resistor1 See Tables 5, 6, and 7 on pg. 3. Loss of Lock indicator output. Asserted when internal PLL is not tracking the input reference for frequency and phase. 3 Logic 1 indicates loss of lock. Logic 0 indicates locked condition. Narrow Bandwidth enable. LVCMOS/LVTTL: Logic 1 - Narrow loop bandwidth, RIN = 2100k . Logic 0 - Wide bandwidth, RIN = 100k . Internal nodes. Connection to these pins can cause erratic device operation.
Table 2: Pin Descriptions
Output
32 34, 35, 36
NBW DNC
Input
Internal pull-UP resistor1 Do Not Connect.
Note 1: For typical values of internal pull-down and pull-UP resistors, see DC Characteristics on pg. 10. Note 2: Biased toVcc/2, with 50k to Vcc and 50k to ground. See Differential Inputs Biased to VCC/2 on pg. 10. Note 3: See LVCMOS Output in DC Characteristics on pg. 10.
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M2060/61/62, M2065/66/67
VCSO FEC PLL FOR SONET/OTN
Preliminary Information
DETAILED BLOCK DIAGRAM
R LOOP C LOOP R POST C POST C POST R LOOP C LOOP OP_OUT R POST nOP_OUT nVC VC
External Loop Filter Components
M2060 Series
NBW LOL
MUX Phase Detector Rfec Div
OP_IN
nOP_IN
Hitless Switching (HS) Opt. HS with Phase Build-out Opt.
R IN
DIF_REF0 nDIF_REF0 DIF_REF1 nDIF_REF1 REF_SEL
0
R IN
1
Loop Filter Amplifier Mfin Divider 1,4,8,32 Options
Phase Locked Loop (PLL)
SAW Delay Line
Phase Shifter
VCSO
Mfec Div
FEC_SEL1:0
Mfec/Rfec Divider LUT P Divider 1,4,8,32 Options TriState
FOUT0 nFOUT0 FOUT1 nFOUT1
FIN_SEL1:0
Mfin Divider LUT P Divider LUT
P_SEL2:0
Figure 3: Detailed Block Diagram
DIVIDER SELECTION TABLES
Mfin Divider Look-Up Tables (LUT) The FIN_SEL1:0 pins select the feedback divider value ("Mfin"), which sets the overall PLL ratio range. Since the VCSO frequency is fixed, this allows input reference selection. The look-up tables vary by device variant.
M2060/61/62: Mfin Value LUT (Includes Divide by 32)
FIN_SEL1:0
Mfec and Rfec Divider Look-Up Tables (LUTs) The FEC_SEL pins select the Mfec/Rfec divider ratio. The look-up tables vary by device variant. The Mfec and Rfec values also establish phase detector frequency. A lower phase detector frequency improves jitter tolerance and lowers loop bandwidth.
M2060/65: FEC Map LUT, OTU1 (255/238) and OTU2 (255/237)
FEC_SEL1:0 Mfec Rfec 10
Description
Mfin Sample Input Reference Freq. (MHz) Options For M20601, M2061 & M20622 Value
Fvcso = Base Input Rate (MHz) Base Output Rate (MHz)
For M2060 or M2065 with Fvcso = 666.5143 (OTU1 FEC rate):
0 0 1 1
0 1 0 1
32 8 4 1
19.44 77.76 155.52 622.08
0 0 1 1
0 1 0 1
15 14 15 15 85 79 85 85
255/238 OC-48 to OTU1 encode OTU1 repeater or jitter attenuator
622.08 666.5143 666.5143 666.5143 622.08 669.3266 669.3266 669.3266
For M2060 or M2065 with Fvcso = 669.3266 (OTU2 FEC rate): 255/237 OC-192 to OTU2 encode OTU2 repeater or jitter attenuator
Table 3: M2060/61/62: Mfin Value LUT (Includes Divide by 32)
Note 1: For M2060 with Fvcso = 666.5143 or 669.3266 Note 2: For M2061 and M2062 with Fvcso = 622.0800.
Table 5: M2060/65: FEC Map LUT, OTU1 (255/238) and OTU2 (255/237)
M2065/66/67: Mfin Value LUT (Includes Divide by 16)
FIN_SEL1:0
M2061/66: FEC De-map LUT, OTU1 (238/255) or OTU2 (237/255)
Mfin Sample Input Reference Freq. (MHz) Options For M20651, M2066 & M20672 Value
Use this option for either OTU1 or OTU2 de-mapping applications, but not both.
FEC_SEL1:0 Mfec Rfec 10
0 0 1 1
0 1 0 1
16 8 4 1
38.88 77.76 155.52 622.08
Description
Fvcso = Base Input Base Output Rate (MHz) Rate (MHz)
For M2061 or M2066 with Fvcso = 622.08 (OTU1 or OTU2 FEC rate):
Table 4: M2065/66/67: Mfin Value LUT (Includes Divide by 16)
0 0 1 1
0 1 0 1
79 85 79 79 14 15 14 14
237/255 OTU2 to OC-192 decode OC-192 repeater or jitter attenuator 238/255 OTU1 to OC-48 decode OC-48 repeater or jitter attenuator
669.3266 622.08 666.5143 622.08
622.08 622.08 622.08 622.08
Note 1: For M2065 with Fvcso = 666.5143 or 669.3266 Note 2: For M2066 and M2067 with Fvcso = 622.0800.
Table 6: M2061/66: FEC De-map LUT, OTU1 (238/255) or OTU2 (237/255)
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M2062/67: FEC De-map LUT, Both OTU1 and OTU2
M2060/61/62, M2065/66/67
VCSO FEC PLL FOR SONET/OTN
Preliminary Information
FUNCTIONAL DESCRIPTION
The M206x Series is a PLL (Phase Locked Loop) based clock generator that generates output clocks synchronized to one of two selectable input reference clocks. An internal high "Q" SAW delay line provides low jitter signal performance and establishes the output frequency of the VCSO (Voltage Controlled SAW Oscillator). In a given M206x Series device, the VCSO center frequency is fixed. A common center frequency is 622.08MHz, for SONET or SDH optical network applications. The VCSO center frequency is specified at time of order (see "Ordering Information" on pg. 12). The VCSO has a guaranteed tuning range of 120 ppm (commercial temperature grade). Pin selectable dividers are used within the PLL and for the output clock. This enables tailoring of device functionality and performance. The FEC feedback and reference dividers (the "Mfec Divider" and "Rfec Divider") provide the multiplication ratios necessary to accomodate clock translation for both forward and inverse Forward Error Correction. The Mfec and Rfec dividers also control the phase detector frequency. The feedback divider (labeled "Mfin Divider") provides the broader division options needed to accomodate various reference clock frequencies. For example, the M2062-11-622.0800 (see "Ordering Information" on pg. 12) has a 622.08MHz VCSO frequency:
Use this option for both OTU1 or OTU2 de-mapping applications. The Mfec divider value is kept nearly constant to maintain similar loop bandwidth using one set of external filter component values.
FEC_SEL1:0 Mfec Rfec 10
Description
Fvcso = Base Input Base Output Rate (MHz) Rate (MHz)
For M2062 or M2067 with Fvcso = 622.08 (OTU1 or OTU2 FEC rate):
0 0 1 1
0 1 0 1
79 85 79 79 84 90 84 84
237/255 OTU2 to OC-192 decode OC-192 repeater or jitter attenuator 238/255 OTU1 to OC-48 decode OC-48 repeater or jitter attenuator
669.3266 622.08 666.5143 622.08
622.08 622.08 622.08 622.08
Table 7: M2062/67: FEC De-map LUT, Both OTU1 and OTU2
P Divider Look-Up Table (LUT) The P_SEL2:0 pins select the P divider values, which set the output clock frequencies. P divider values of 1, 4, 8, or 32 are available, plus a TriState mode. A P divider of value of 1 will provide a 669.3266MHz output when using a 669.3266MHz VCSO, for example. The outputs can be placed into the valid state combinations as listed in Table 8. (They cannot be set independently to any of the available output frequencies.)
P Value
P_SEL2:0
M2060-622.0800 or M2065-622.0800
for FOUT0 for FOUT1 32 1 32 4 1 1 4 1 8 8 4 4 8 4 TriState TriState
Output Frequency (MHz)
FOUT0 FOUT1
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
19.44 19.44 622.08 155.52 77.76 155.52 77.76 N/A
622.08 155.52 622.08 622.08 77.76 155.52 155.52 N/A
* The FEC de-mapper PLL ratios (in Tables 6 and 7)
enable the M2062-11-622.0800 to accept "base" input reference frequencies of: 666.5143 (OTU1), 669.3266 (OTU2), and 622.08MHz (OC-192). * The Mfin feedback divider enables the actual input reference clock to be the base input frequency divided by 1, 4, 8, or 32 (or 16). Therefore, for the base input frequency of 622.08MHz, the actual input reference clock frequencies can be: 622.08, 155.52, 77.76, and 19.44 or 38.88MHz. (See Tables 3 and 4 on pg. 3.) Key to Device Variants and Look-up Table Options
Device Variant M2060 M2061 M2062 M2065 M2066 M2067 Look-up Table Option Mfin Lookup Table is: Mfec Look-up Table is: Table 5 (FEC mapper LUT) Table 3 Table 6 (FEC de-mapper LUT) (includes divider value 32) Table 7 (FEC de-mapper LUT) Table 5 (FEC mapper LUT) Table 4 Table 6 (FEC de-mapper LUT) (includes divider value 16) Table 7 (FEC de-mapper LUT)
Table 9: Key to Device Variants and Look-up Table Options
Table 8: P Divider Look-Up Table (LUT)
General Guidelines for Phase Detector Frequency
The phase detector frequency (Fpd) is equal to the input reference frequency (Fref) divided by the Rfec divider value, or: Fpd = Fref / Rfec General guidelines: * A lower phase detector frequency should be used for loop timing applications to assure PLL tracking, especially during GR-253 jitter tolerance testing. The recommended maximum phase detector frequency for loop timing mode is 19.44MHz. * When LOL is to be used for system health monitoring, the phase detector frequency should be 5MHz or greater. Low phase detector frequencies make LOL overly sensitive, and higher phase detector frequencies make LOL less sensitive. The LOL pin should not be used during loop timing mode.
M2060/61/62 M2065/66/67 Datasheet Rev 0.4 Integrated Circuit Systems, Inc.
The P divider scales the VCSO output enabling lower output frequency selections (Table 8).
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The M206x Series includes a Loss of Lock (LOL) indicator, which provides status information to system management software. A Narrow Bandwidth (NBW) control pin is provided as an additional mechanism for adjusting PLL loop bandwidth without affecting the phase detector frequency. Options are available for Hitless Switching (HS) with or without Phase Build-out (PBO). They provide SONET/ SDH MTIE and TDEV compliance during a reference clock reselection. Input Reference Clocks Two clock reference inputs and a selection mux is provided. Either reference clock input can accept a differential clock signal (such as LVPECL or LVDS) or a single-ended clock input (LVCMOS or LVTTL on the non-inverting input).
A single-ended reference clock on the unselected reference input can cause an increase in output clock jitter. For this reason, differential reference inputs are preferred; interference from a differential input on the non-selected input is minimal.
M2060/61/62, M2065/66/67
VCSO FEC PLL FOR SONET/OTN
Preliminary Information
Differential Inputs
Differential LVPECL inputs are connected to both reference input pins in the usual manner. The external load termination resistors shown in Figure 4 (the 127 and 82 resistors) is ideally suited for both AC and DC coupled LVPECL reference clock lines. These provide the 50 load termination and the VTT bias voltage.
Single-ended Inputs
Single-ended inputs (LVCMOS or LVTTL) are connected to the non-inverting reference input pin (DIF_REF0 or DIF_REF1). The inverting reference input pin (nDIF_REF0 or nDIF_REF1) must be left unconnected.
In single-ended operation, when the unused inverting input pin (nDIF_REF0 or nDEF_REF1) is left floating (not connected), the input will self-bias at VCC/2.
PLL Operation The M2060/61/62 and M2065/66/67 are complete clock PLLs. They use a phase detector and configurable dividers to synchronize the output of the VCSO with the selected reference clock. The PLL will work correctly, meaning it will phase-lock the VCSO output to the input reference clock, when the internal phase detector inputs are able to run at the same frequency. This means the PLL dividers must be set appropriately and a suitable reference frequency must be chosen for the intended output frequency. When the PLL is not set up appropriately, the VCSO is forced to its upper or lower operating limit which is typically about 200 ppm above or below the VCSO center frequency. See "APR, VCSO Absolute Pull-Range" row, in the AC Characteristics table on pg. 11. In normal phase-locked condition, the instantaneous phase error is measured by the phase detector and is converted to charge pump current pulses. These current pulses are then integrated by the external loop filter to create a VCSO control voltage. The loop filter acts as a low pass filter to remove unwanted reference clock jitter above a determined frequency or PLL bandwidth. For reference phase jitter frequencies within the loop bandwidth, phase jitter amplitude is passed on to the output clock according to the PLL loop frequency response curve. The relationship between the nominal VCSO center frequency (Fvcso), the Mfin divider, the Mfec divider, the Rfec divider, and the input reference frequency (Fin) is: Mfec Fvcso = Fin x Mfin x ------------Rfec
Configuration of a single-ended input has been facilitated by biasing nDIF_REF0 and nDEF_REF1 to Vcc/2, with 50k to Vcc and 50k to ground. The input clock structure, and how it is used with either LVCMOS/LVTTL inputs or a DC- coupled LVPECL clock, is shown in Figure 4.
.
DIF_REF0
50k VCC 50k X 50k MUX
LVCMOS/ LVTTL
nDIF_REF0
VCC
0
DIF_REF1
LVPECL
127 VCC 127 VCC 50k
1
82
50k
nDIF_REF1 REF_SEL
82
50k
Figure 4: Input Reference Clocks
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The Mfec, Rfec, and Mfin dividers can be set by pin configuration using the input pins FEC_SEL1, FEC_SEL0, FIN_SEL1, and FIN_SEL0. Post-PLL Divider The M2060/61/62 and M2065/66/67 also feature a post-PLL (P) divider. Through use of the P divider, the device's output frequency (Fout) can be that of the VCSO (such as 622.08MHz) or the VCSO frequency divided by 4, 8 or 32 (common optical reference clocks in SONET and SDH systems). The P_SEL2:0 pins select the value for the P divider. (See Table 8 on pg. 4.) Accounting for the P divider, the complete relationship between the input clock reference frequency (Fin) and output clock frequency (Fout) is defined as: Mfin x Mfec Fvcso Fout = ------------------- = Fin x --------------------------------P Rfec x P
M2060/61/62, M2065/66/67
VCSO FEC PLL FOR SONET/OTN
Preliminary Information Loss of Lock Indicator (LOL) Output Pin Under normal device operation, when the PLL is locked, the LOL Phase Detector drives LOL to logic 0. Under circumstances when the VCSO cannot fully phase lock to the input (as measured by a greater than 4 ns discrepancy between the feedback and reference clock rising edges at the LOL Phase Detector) the LOL output goes to logic 1. The LOL pin will return back to logic 0 when the phase detector error is less than 2 ns. The loss of lock indicator is a low current LVCMOS output.
Guidelines for Using LOL
Due to the narrow tuning range of the VCSO (+120ppm guaranteed), appropriate selection of all of the following are required for the PLL be able to lock: VCSO center frequency, input frequency, and divider selections. TriState The TriState feature puts the LVPECL output driver into a high impedance state, effectively disconnecting the driver from the FOUT and nFOUT pins of the device. In TriState, the M206x Series is not driving the output clock net with a defined logic level. The impedance of the clock net is then set to 50 by the external circuit resistors. The 50 impedance level of the LVPECL TriState allows manufacturing In-circuit Test to drive the clock net with an external LVPECL source to validate the integrity of clock net and the clock load.
Any unused output (single-ended or differential) should be left unconnected (floating) in system application. This minimizes output switching current and therefore minimizes noise modulation of the VCSO.
In a given application, the magnitude of peak-to-peak jitter at the phase detector will usually increase as the Rfec divider is increased. If the LOL pin will be used to detect an unusual clock condition, or a clock fault, the FEC_SEL1:0 pins should be set to provide a phase detector frequency of 5MHz or greater (the phase detector frequency is equal to Fin divided by the Rfec divider). Otherwise, false LOL indications may result. A phase detector frequency of 10MHz or greater is desirable when reference jitter is over 500ps, or when the device is used within a noisy system environment. LOL should not be used when the device is used in a loop timing application.
Narrow Bandwidth (NBW) Control Pin A Narrow Loop Bandwidth control pin (NBW pin) is included to enable adjustment of the PLL loop bandwidth. In wide bandwidth mode (NBW=0), the internal resistor Rin is 100k . With the NBW pin asserted (NBW=1), the internal resistor Rin is changed to 2100k . This lowers the loop bandwidth by a factor of about 21 (2100 / 100) and lowers the damping factor by about 4.6 (the square root of 21), assuming the same external loop filter component values.
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Optional Hitless Switching and Phase Build-out The M206x Series is available with a Hitless Switching feature that is enabled during device manufacturing. In addition, a Phase Build-out feature is also offered. These features are offered as device options and are specified by device order code. Refer to "Ordering Information" on pg. 12. The Hitless Switching feature (with or without Phase Build-out) is designed for applications where switching occurs between two stable system reference clocks. It should not be used in loop timing applications, or when reference clock jitter is greater than 1 ns pk-pk. The Hitless Switching sequence is triggered by the LOL circuit, which is activated by a 4 ns phase transient. This magnitude of phase transient can generated by the CDR (Clock & Data Recovery unit) in loop timing mode, especially during a system jitter tolerance test. It can also be generated by some types of Stratum clock DPLLs (digital PLL), especially those that do not include a post de-jitter APLL (analog PLL). When the M206x Series is operating in wide bandwidth mode (NBW=0), the optional Hitless Switching function puts the device into narrow bandwidth mode during the Hitless Switching sequence. This allows the PLL to lock the new input clock phase gradually. With proper configuration of the external loop filter, the output clock phase change complies with MTIE and TDEV specifications for GR-253 (SONET) and ITU G.813 (SDH) during input reference clock changes. The optional proprietary Phase Build-out (PBO) function enables the PLL to absorb most of the phase change of the input clock during reference switching. The PBO function selects a new VCSO clock edge for the PLL Phase Detector feedback clock, selecting the edge closest in phase to the new input clock phase. This reduces re-lock time, the generation of wander, and extra output clock cycles. The Hitless Switching and Phase Build-out functions are triggered by the LOL circuit. For proper operation, a low phase detector frequency must be avoided. See "Guidelines for Using LOL" on pg. 6 for information regarding the phase detector frequency.
HS/PBO Sequence Trigger Mechanism
M2060/61/62, M2065/66/67
VCSO FEC PLL FOR SONET/OTN
Preliminary Information
HS/PBO Operation
Once triggered, the following HS/PBO sequence occurs: 1. The HS function disables the PLL Phase Detector and puts the device into NBW (narrow bandwidth) mode. The internal resistor Rin is changed to 2100k . See Narrow Bandwidth (NBW) Control Pin on pg. 6. 2. If included, the PBO function adds to (builds out) the phase in the clock feedback path (in VCSO clock cycle increments) to align the feedback clock with the (new) reference clock input phase. 3. The PLL Phase Detector is enabled, allowing the PLL to re-lock. 4. Once the PLL Phase Detector feedback and input clocks are locked to within 2 nsec for 8 consecutive cycles, a timer (WBW timer) for resuming wide bandwidth (in 175 nsec) is started. 5. When the WBW timer times out, the device reverts to wide loop bandwidth mode (i.e., Rin is returned to 100k) and the HS/PBO function is re-armed. The LOL pin will indicate lock status on a cycle-to-cycle basis and may be intermittent until PLL phase lock has fully stabilized.
The HS function (or the combined HS/PBO function) is armed after the device locks to the input clock reference. Once armed, HS is triggered by the occurance of a Loss of Lock condition. This would typically occur as a consequence of a clock reference failure, a clock failure upstream to the M206x Series, or a M206x Series clock reference mux reselection.
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External Loop Filter To provide stable PLL operation, the M2060/61/62 or M2065/66/67 requires use of an external loop filter. This is provided via the provided filter pins (see Figure 5). The loop filter is implemented as a differential circuit to minimize system noise interference.
RLOOP CLOOP RPOST CPOST CPOST RLOOP OP_IN
4 9
M2060/61/62, M2065/66/67
VCSO FEC PLL FOR SONET/OTN
Preliminary Information
CLOOP OP_OUT
8 5
RPOST nOP_OUT nVC
6 7
nOP_IN
VC
Figure 5: External Loop Filter
PLL bandwidth is affected by loop filter component values, "Mfec" and "Mfin" values, and the "PLL Loop Constants" listed in AC Characteristics on pg. 11. The FEC_SEL setting can be used to actively change PLL loop bandwidth in a given application. See "Mfec and Rfec Divider Look-Up Tables (LUTs)" on pg. 3. See Table 10, Example Values for Loop Filter External Components, on pg. 8. PLL Simulator Tool Available A free PC software utility is available on the ICS website (www.icst.com). The M2000 Timing Modules PLL Simulator is a downloadable application that simulates PLL jitter and wander transfer characteristics. This enables the user to set appropriate external loop component values in a given application. Example Values for Loop Filter External Components 1 for Particular M206x Series Devices
VCSO Parameters: KVCO = 800kHz/V, RIN = 100k (pin NBW = 0), VCSO Bandwidth = 700kHz. Device Device Configuration FVCSO FIN_SEL MRSEL 1:0 1:0 (MHz) (MHz) Example External Component Values Nominal Performance With These Values
FRef
R loop 5.6k
C loop 10F 0.1F 10F 10F
R post 68k 34k 100k 100k
C post 470pF 470pF 470pF 470pF
PLL Loop Damping Passband Bandwidth Factor Peaking (dB) 530Hz 1kHz 360Hz 360Hz 6.5 5.9 6.5 6.5 0.05 0.06 0.05 0.05
M2060, M2060 622.08 M2060, M2065 155.52 M2061, M2066 M2061
622.08 669.3266 622.08 622.08
11 10 01 00
01
77.76 19.44
1 0 0243.0k 01 8.2k 11 8.2k
Table 10: Example Values for Loop Filter External Components
Note 1: KVCO , VCSO Bandwidth, M Divider Value, and External Loop Filter Component Values determine Loop Bandwidth, Damping Factor, and Passband Peaking. For PLL Simulator software, go to www.icst.com.
Refer to the M206x Series product web page at www.icst.com/products/summary/M2060-2067.htm for additional product information.
M2060/61/62 M2065/66/67 Datasheet Rev 0.4 Integrated Circuit Systems, Inc.
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VCSO FEC PLL FOR SONET/OTN
Preliminary Information
ABSOLUTE MAXIMUM RATINGS1
Symbol Parameter Rating Unit
VI VO VCC TS
Inputs Outputs Power Supply Voltage Storage Temperature
-0.5 to VCC +0.5 -0.5 to VCC +0.5
4.6
V V V
o
-45 to +100
C
Table 11: Absolute Maximum Ratings
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in Recommended Conditions of Operation, DC Characteristics, or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
RECOMMENDED CONDITIONS OF OPERATION
Symbol Parameter Min 3.135 Typ 3.3 Max 3.465 Unit
VCC TA
Positive Supply Voltage Ambient Operating Temperature Commercial Industrial
V
oC oC
0 -40
+70 +85
Table 12: Recommended Conditions of Operation
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M2060/61/62, M2065/66/67
VCSO FEC PLL FOR SONET/OTN
Preliminary Information
ELECTRICAL SPECIFICATIONS
DC Characteristics
Unless stated otherwise, VCC = 3.3V +5%,TA = 0 oC to +70 oC (commercial), TA = -40 oC to +85 oC (industrial), FVCSO = FOUT = 622-675MHz, LVPECL outputs terminated with 50 to VCC - 2V
Symbol Parameter
Min 3.135
Typ 3.3 175
Max 3.465 225
Unit Conditions
Power Supply VCC ICC All Differential Inputs Differential Inputs with Pull-down Differential Inputs Biased to VCC/2 1 All LVCMOS / LVTTL Inputs LVCMOS / LVTTL Inputs with Pull-down LVCMOS / LVTTL Inputs with Pull-UP Differential Outputs VP-P VCMR CIN IIH IIL IIH IIL Rbias VIH VIL CIN IIH IIL IIH IIL Rpullup VOH VOL VP-P LVCMOS Output VOH VOL
Positive Supply Voltage Power Supply Current Peak to Peak Input Voltage Common Mode Input Input Capacitance Input High Current (Pull-down) Input Low Current (Pull-down) Input High Current (Biased) 1 Input Low Current (Biased) Biased to Vcc/2 1 Input High Voltage Input Low Voltage Input Capacitance Input High Current (Pull-down) Input Low Current (Pull-down) Input High Current (Pull-UP) Input Low Current (Pull-UP) Internal Pull-UP Resistance Output High Voltage Output Low Voltage Peak to Peak Output Voltage Output High Voltage Output Low Voltage
2
1
V mA V
0.15 DIF_REF0, nDIF_REF0, DIF_REF1, nDIF_REF1 0.5
Vcc - .85 V 4 150
pF A A k
VCC = VIN = 3.456V
DIF_REF0, DIF_REF1
-5
50 150
Rpulldown Internal Pull-down Resistance
nDIF_REF0, nDIF_REF1
A A k
-150
(Note 1) 2
VIN = 0 to 3.456V
REF_SEL, FIN_SEL1, FIN_SEL0, FEC_SEL1, FEC_SEL0, P_SEL2, P_SEL1, P_SEL0, NBW REF_SEL, FIN_SEL1, FIN_SEL0, FEC_SEL1, FEC_SEL0, P_SEL2, P_SEL1, P_SEL0
Vcc + 0.3 V 0.8 4 150
-0.3
V pF A A k
VCC = VIN = 3.456V
-5
50
Rpulldown Internal Pull-down Resistance
5
NBW
A A k
-150
50 Vcc - 1.4 Vcc - 2.0 0.4 2.4
VCC = 3.456V VIN = 0 V
FOUT0, nFOUT0, FOUT1, nFOUT1
Vcc - 1.0 V Vcc - 1.7 V 0.85
V V V IOH= 1mA IOL= 1mA
LOL GND
VCC
0.4
Note 1: Biased to Vcc/2, with 50k to Vcc and 50k to ground. See Figure 4, Input Reference Clocks, on pg. 5 Note 2: Single-ended measurement. See Figure 6, Output Rise and Fall Time, on pg. 11.
Table 13: DC Characteristics
M2060/61/62 M2065/66/67 Datasheet Rev 0.4 Integrated Circuit Systems, Inc.
10 of 12
Revised 30Jul2004 w w w. i c s t . c o m
Networking & Communications
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Integrated Circuit Systems, Inc.
M2060/61/62, M2065/66/67
VCSO FEC PLL FOR SONET/OTN
Preliminary Information
ELECTRICAL SPECIFICATIONS (CONTINUED)
AC Characteristics
Unless stated otherwise, VCC = 3.3V +5%,TA = 0 oC to +70 oC (commercial), TA = -40 oC to +85 oC (industrial), FVCSO = FOUT = 622-675MHz, LVPECL outputs terminated with 50 to VCC - 2V
Symbol Parameter
Min DIF_REF0, nDIF_REF0, DIF_REF1, nDIF_REF1 FOUT0, nFOUT0, FOUT1, nFOUT1 Commercial Industrial 10 15
Typ
Max 700 700
Unit Conditions
FIN FOUT APR KVCO PLL Loop Constants 1 RIN
Input Frequency Output Frequency VCSO Absolute Pull-Range VCO Gain Internal Loop Resistor
MHz MHz ppm ppm kHz/V k k kHz dBc/Hz Fin=19.44 or dBc/Hz Mfin=32 (or 16), dBc/Hz Mfec=Rfec
38.88 MHz
120 50
200 150
800 100 2100 700
Wide Bandwidth Narrow Bandwidth
BWVCSO VCSO Bandwidth n Phase Noise and Jitter J(t) odc tR tF Single Side Band Phase Noise @622.08MHz Jitter (rms) @622.08MHz Output Duty Cycle 2
FOUT0, nFOUT0, FOUT1, nFOUT1 1kHz Offset 10kHz Offset 100kHz Offset 12kHz to 20MHz 50kHz to 80MHz
P = 4, 8, or 32 P=1 2
-73 -103 -126
0.25 0.25 45 40 200 50 50 450 450 0.5 0.5 55 60 500 500
ps ps % % ps ps
20% to 80% 20% to 80%
Output Rise Time Output Fall Time
2
FOUT0, nFOUT0, FOUT1, nFOUT1 200
Table 14: AC Characteristics
Note 1: Parameters needed for PLL Simulator software; see Table 10, Example Values for Loop Filter External Components, on pg. 8. Note 2: See Parameter Measurement Information on pg. 11.
PARAMETER MEASUREMENT INFORMATION
Output Rise and Fall Time Output Duty Cycle
nFOUT FOUT VP-P Clock Output 20% tR 20% tF odc = tPW tPERIOD tPW (Output Pulse Width) tPERIOD
80%
80%
Figure 6: Output Rise and Fall Time
Figure 7: Output Duty Cycle
M2060/61/62 M2065/66/67 Datasheet Rev 0.4 Integrated Circuit Systems, Inc.
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Preliminary Information
M2060/61/62, M2065/66/67
VCSO FEC PLL FOR SONET/OTN
DEVICE PACKAGE - 9 x 9mm CERAMIC LEADLESS CHIP CARRIER
Mechanical Dimensions:
Refer to the M206x Series product web page at www.icst.com/products/summary/M2060-2067.htm for recommended PCB footprint, solder mask, furnace profile, and related information.
Figure 8: Device Package - 9 x 9mm Ceramic Leadless Chip Carrier
ORDERING INFORMATION
Part Numbering Scheme Part Number:
Divider Look-up Table Option See Table 9, page 4. Output type 1 = LVPECL (For CML or LVDS clock output, consult factory) Hitless Switching / Phase Build-out Options 1 = none 2 = Hitless Switching 3 = Hitless Switching with Phase Build-out Temperature " - " = 0 to +70 oC (commercial) I = - 40 to +85 oC (industrial) VCSO Frequency (MHz) See Table 15, right. Consult ICS for other frequencies.
Standard VCSO Output Frequencies (MHz)* 622.0800 669.3120 669.3266 669.6429 670.8386 672.1600 690.5692
M206x- yz - xxx.xxxx
625.0000 627.3296 644.5313 666.5143 669.1281
Table 15: Standard VCSO Output Frequencies
Figure 9: Part Numbering Scheme
Note *: Fout can equal Fvcso divided by: 1, 4, 8, or 32.
Consult ICS for the availability of other VCSO frequencies.
Example Part Numbers
VCSO Frequency (MHz) Temperature 622.0800 669.3266
commercial industrial commercial industrial
Order Part Number (Examples) M2061 - 11 - 622.0800 or M2062- 11 - 622.0800 M2061 - 11I 622.0800 or M2062- 11I 622.0800 M2060 - 11 - 669.3266 or M2065 - 11 - 669.3266 M2060 - 11I 669.3266 or M2065- 11I 669.3266
Table 16: Example Part Numbers
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. M2060/61/62 M2065/66/67 Datasheet Rev 0.4 Integrated Circuit Systems, Inc.
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